You’re dsPICable!

Ya, dodged work along with junior-senior-engineer(?) G* to attend a tech seminar on the dsPIC micro/DSP rolled into one. Getting paid to dodge work (w/ blessing) is nice. Not really much to write about this, so this is here mainly for the timestamp. All right, just one bit because it amused me. The dsPIC core innards were described as being a “modified Harvard architecture”, except with no cache, no pipeline, and no separate code/data memories. I guess that in particular doesn’t matter for this chip (the entire memory space, all 2k ~ 8k of it, is essentially on-chip registers, and all fetch in 1 instruction cycle anyway); still, it did kind of sound like it was defeating the purpose of harvard arch, and gave me the inexplicable mental image of someone ordering a Big Mac “hold the cheese, meat, lettuce and bun” :-)

QOTD: “Who in the hell would want four wives? I’ve only got one neck. Where am I going to put the other three pains?” – Seen on


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